Clock data recovery (CDR) circuits are often used in high speed signaling applications to recover clock and data signals from a signal line. Typically, transitions in an incoming signal are detected and used to generate a clock signal which is used, in turn, to sample data in the incoming signal.
FIG. 1 illustrates a prior art transceiver device 100 that includes a CDR circuit 101, phase locked-loop (PLL) circuit 103, transmit circuit 105 and application logic 107. The PLL circuit 103 outputs a transmit clock (TCLK) to the transmit circuit 105 and a set of eight clock signals, referred to as phase vectors (PV), to the CDR circuit 101. Data recovered by the CDR circuit 101 is provided to the application logic 107 as receive data, and the application logic 107 outputs data to the transmit circuit 105 to transmit the data via a data output path in response to the transmit clock.
In the circuit of FIG. 1, the phase vectors generated by the PLL circuit 103 are offset from one another by successive 45 degree increments such that, considering an arbitrary one of the phase vectors to have a zero degree phase angle, the remaining seven phase vectors have phase angles of 45, 90, 135, 180, 225, 270, and 315 degrees. The phase mixer 113 selects and interpolates between a pair of the phase vectors according to a phase count value to produce a recovered clock signal, RCLK.
The receive circuit 115 captures a number of samples of the incoming data signal during each cycle of the recovered clock signal. The samples are compared with one another within the phase control circuit 111 to determine whether transitions in the incoming data signal occur early or late relative to edges of the recovered clock signal. Based on the early/late determination, the phase control circuit 111 outputs a control signal (U/D) to the phase mixer 115 which responds by increasing or decreasing the phase count value and thereby delaying or advancing the phase of the recovered clock signal. Eventually, the CDR circuit 101 reaches a phase locked condition in which the recovered clock signal has a desired phase relationship to the incoming data signal (e.g., a sampling clock component of the recovered clock signal becomes aligned with the midpoint of data valid intervals of the input signal), and the phase control circuit 111 begins to toggle the control signal between advancing and delaying the phase of the recovered clock signal.
One limitation of the transceiver device 100 is that the CDR circuit 101 and PLL circuit 103 are usually tuned to a particular input data rate. More specifically, the phase-locked frequency of the recovered clock signal is typically limited to a frequency band centered around the PLL output clock frequency (i.e., frequency of the phase vectors) such that, if the data rate falls outside the frequency band, the CDR circuit 101 will be unable to achieve phase lock. In applications where the transceiver device need only support a single input data rate, phase locking of the CDR circuit may be ensured by specifying the PLL output clock frequency and the frequency of the clock used to generate the input data signal (thereby setting the data rate) to be within a predetermined tolerance. Difficulties arise, however, in applications where the transceiver device 100 must support more than one data rate.
The most direct solution to supporting multiple input data rates within the transceiver device 100 is to design the PLL circuit 103 to support a wide range of reference clock frequencies, thereby permitting a wide range of PLL output clock frequencies and a wide band operation of the CDR circuit 101. Unfortunately, wide-range PLL circuits typically exhibit compromised clock fidelity (e.g. increased clock jitter) and therefore tend to be inferior to PLL circuits designed for a narrower frequency range. An alternative solution for supporting multiple input data rates is to use multiple PLL circuits, each optimized for a different input data rate. The disadvantage of this approach is that the increased power, die area, and design effort of the additional PLL circuit(s) make the resulting device more expensive to produce and operate. Thus, it would be desirable to provide a transceiver device that can support multiple input data rates without requiring multiple PLL circuits and without compromising high speed clock performance.